Autores
Ramírez Salinas Marco Antonio
Villa Vargas Luis Alfonso
Leyva Santes Neiel Israel
Hernández Calderón César Alejandro
Rojas Morales Carlos
Título Automatic code generator for a customized high performance microprocessor simulator
Tipo Congreso
Sub-tipo Memoria
Descripción 9th International Conference on Supercomputing, ISUM 2018
Resumen This paper presents a software that generates code that implements a microprocessor simulator based on features defined by user. Software receives a set of microprocessor architecture description that includes: number of cores, operations to be executed in the ALU, cache memory details, and number of registers, among others. After configuration, the software generates Java code that implements the microprocessor simulator described. Software can generates more than forty different codes depending on the configurations defined. Each simulator follows a standard four stages pipeline: fetch, decode, execute and store. Code generator has been used as a learning tool in an undergraduate course with interesting effects in the student’s learning process. Preliminary results show that students understand better how a microprocessor works and they felt ready to propose new microprocessor architectures.
Observaciones doi: 10.1007/978-3-030-10448-1_2
Lugar Mérida
País Mexico
No. de páginas 11-23
Vol. / Cap.
Inicio 2019-03-05
Fin 2019-03-09
ISBN/ISSN 978-303010447-4