Autores
Hernández Calderón César Alejandro
Leyva Santes Neiel Israel
Ramírez Salinas Marco Antonio
Villa Vargas Francisco Javier
Título DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
Tipo Congreso
Sub-tipo Memoria
Descripción 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022
Resumen This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology. © 2022 IEEE.
Observaciones DOI 10.1109/DCIS55711.2022.9970128
Lugar Pamplona
País España
No. de páginas
Vol. / Cap.
Inicio 2022-11-16
Fin 2022-11-18
ISBN/ISSN 9781665459501