| Autores |
|---|
| Hernández Calderón César Alejandro |
| Leyva Santes Neiel Israel |
| Ramírez Salinas Marco Antonio |
| Villa Vargas Luis Alfonso |
| Título | Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology |
| Tipo | Congreso |
| Sub-tipo | Memoria |
| Descripción | 38th Conference on Design of Circuits and Integrated Systems, DCIS 2023 |
| Resumen | This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM (CSIC). The SoC includes the processor as well as, among other components, a Phase Locked Loop (PLL) operating up to 2 GHz, interfaces to HyperRAM and a Serdes up to 8 Gbps. The processor has demonstrated experimental correct operation at 800 MHz. © 2023 IEEE. |
| Observaciones | DOI 10.1109/DCIS58620.2023.10335976 |
| Lugar | Málaga |
| País | España |
| No. de páginas | |
| Vol. / Cap. | |
| Inicio | 2023-11-15 |
| Fin | 2023-11-17 |
| ISBN/ISSN | 9798350303858 |